The technical field of this invention is digital device functional blocks, used generally in the area of microprocessor design and more specifically in the area of digital signal processor devices.
The transfer controller with hub and ports architecture (TCHP), which is the subject of U.S. patent application Ser. No. 09/543,870 filed Apr. 6, 2000, now U.S. Pat. No. 6,496,740, is referenced in this text and referred to as simply a centralized transaction processor (CTP). This centralized transaction processor is a significant basic improvement in data transfer techniques in complex digital systems. Along with many other features, the centralized transaction processor allows for uniform implementation of port interfaces at the periphery of such systems. Features of the centralized transaction processor are enhanced when combined with an advanced direct memory access (DMA) processor such as external direct memory access processor external direct memory access of this invention.
The centralized transaction processor functional blocks and their interconnection to the external direct memory access processor are illustrated in the high level diagram of FIG. 1. The centralized transaction processor implementation and feature set are for the most part independent of the external direct memory access, functionality. The centralized transaction processor is comprised of hub 100 and ports 111 through 115. It performs the following tasks:
(1) Receives transfer requests in the form of transfer request packets 103 from transfer requester nodes 116 which communicate with the transfer request bus 117; the external direct memory access processor is one of those transfer requesters;
(2) Places these requests in queue manager RAM 102 within the TCHP hub 100;
(3) Prioritizes them by placing them in one of several priority levels within the TCHP hub channel registers 120;
(4) Generates source (read) and destination (write) commands and data for output from the source pipeline 121 and destination pipeline 122;
(5) Broadcasts these source and destination commands and data to all ports 111-115;
(6) Receives read data, acknowledge/status information from ports through the data router 123;
(7) Generates new source (read) and destination (write) commands and data for output from the source pipeline 121 and destination pipeline 122 to the I/O subsystem 123.
The external direct memory access processor of the present invention performs a super-set of the functions of a conventional DMA. The external direct memory access of this invention also provides all the features
of the most advanced DMA functions including a full complement of transfer types plus support for a large number of channels. In addition, the external direct memory access architecture is both scalable and flexible without adding significant hardware for increasing the number of channels or modes supported.
Functionally, the external direct memory access processor consists of three main parts. The first part is the event capture and prioritization logic which serves to handle input requests and channel management. The event capture and prioritization logic continuously monitors the incoming requests for N-channels of the external direct memory access. Additionally, it is responsible for responding to these requests by submitting transfer requests to the second portion of the processor, the external direct memory access controller.
External requests might include, but are not limited to, external interrupts routed directly to the external direct memory access processor, on-chip peripherals not serviced in real time by the CPU, and more intelligent mastering peripherals or host CPUs. Mastering peripherals are characterized by their the ability to actively control transaction processing.
The third portion of the external direct memory access processor is the parameter RAM. The parameter RAM is generically the storage facility for the external direct memory access parameters. Because many complex tasks are supported, a high density RAM is very important to the external direct memory access architecture.
The external direct memory access controller performs a superset of all the functions of a conventional DMA. In addition the architecture of the external direct memory access lends itself to a much more scalable and easily maintainable design. Feature enhancements such as new transfer types, or number of events supported, are far simpler to add to the external direct memory access architecture than to a conventional DMA.